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DESCRIPTION
The WM8955L is a low power, high quality stereo DAC with integrated headphone and loudspeaker amplifiers, designed to reduce external component requirements in portable digital audio applications. The on-chip headphone amplifiers can deliver 40mW into a 16 load. Advanced on-chip digital signal processing performs bass and treble tone control. The WM8955L can operate as a master or a slave, and includes an on-chip PLL. It can use most master clock frequencies commonly found in portable systems, including USB, GSM, CDMA or PDC clocks, or standard 256fs clock rates. Different audio sample rates such as 48kHz, 44.1kHz, 8kHz and many others are supported. The WM8955L operates on supply voltages from 1.8V up to 3.6V, although the digital core can operate on a separate supply down to 1.42V, saving power. Different sections of the chip can also be powered down under software control. The WM8955L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems.
WM8955L
Stereo DAC For Portable Audio Applications
FEATURES
* * * * * * * * * * * DAC SNR 98dB, THD -86dB (`A' weighted @ 48kHz, 3.3V) On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver - 40mW output power on 16 / 3.3V - SNR 96dB, THD -79dB at 20mW with 16 load Stereo and Mono Line-in mix into DAC output Separately Mixed Stereo and Mono Outputs Digital Tone Control and Bass Boost Low Power - Down to 7mW for stereo playback (1.8V / 1.5V supplies) - 10W Shutdown Mode Low Supply Voltages - Analogue and Digital I/O: 1.8V to 3.6V - Digital core: 1.42V to 3.6V Master clocks supported: GSM, CDMA, PDC, USB or standard audio clocks Audio sample rates supported: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz 32-lead QFN package, 5x5x0.9mm size, 0.5mm lead pitch
APPLICATIONS
* * Smartphone / Multimedia Phone Digital Audio Player
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, March 2006, Rev 4.2 Copyright 2006 Wolfson Microelectronics plc
WM8955L TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................. 7 OUTPUT PGA'S LINEARITY ......................................................................................... 8 HEADPHONE OUTPUT THD VERSUS POWER........................................................... 9 SPEAKER THD AND NOISE VERSUS POWER ......................................................... 10
POWER CONSUMPTION ....................................................................................11 AUDIO PATHS OVERVIEW .................................................................................12 SIGNAL TIMING REQUIREMENTS .....................................................................13
SYSTEM CLOCK TIMING............................................................................................ 13 AUDIO INTERFACE TIMING - MASTER MODE ......................................................... 13 AUDIO INTERFACE TIMING - SLAVE MODE ............................................................ 14 CONTROL INTERFACE TIMING - 3-WIRE MODE ..................................................... 14 CONTROL INTERFACE TIMING - 2-WIRE MODE ..................................................... 15
INTERNAL POWER ON RESET CIRCUIT ..........................................................16 DEVICE DESCRIPTION.......................................................................................17
INTRODUCTION.......................................................................................................... 17 SIGNAL PATH ............................................................................................................. 17 LINE INPUTS AND OUTPUT MIXERS ........................................................................ 21 ANALOGUE OUTPUTS ............................................................................................... 24 DIGITAL AUDIO INTERFACE...................................................................................... 28 MASTER CLOCK AND PHASE LOCKED LOOP ......................................................... 31 AUDIO SAMPLE RATES.............................................................................................. 33 CONTROL INTERFACE .............................................................................................. 35 POWER SUPPLIES ..................................................................................................... 36 POWER MANAGEMENT ............................................................................................. 37
REGISTER MAP...................................................................................................39 DIGITAL FILTER CHARACTERISTICS ...............................................................40
TERMINOLOGY........................................................................................................... 40 DAC FILTER RESPONSES ......................................................................................... 40
APPLICATIONS INFORMATION .........................................................................42
RECOMMENDED EXTERNAL COMPONENTS........................................................... 42 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS ........................................ 43 LINE OUTPUT CONFIGURATION............................................................................... 43 HEADPHONE OUTPUT CONFIGURATION ................................................................ 44 SPEAKER OUTPUT CONFIGURATION...................................................................... 44
PACKAGE DIMENSIONS ....................................................................................45 IMPORTANT NOTICE ..........................................................................................46
ADDRESS:................................................................................................................... 46
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WM8955L
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE WM8955LSEFL TEMPERATURE RANGE -25C to +85C PACKAGE 32-lead QFN (5x5x0.9mm) (Pb-free) 32-lead QFN (5x5x0.9mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC
WM8955LSEFL/R
-25C to +85C
MSL1
Note: Reel quantity = 3,500
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WM8955L PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME MCLK DCVDD DBVDD DGND BCLK DACDAT DACLRC CLKOUT PLLGND MONOOUT OUT3 ROUT1 LOUT1 HPGND ROUT2 LOUT2 HPVDD AVDD AGND VREF VMID NC HPDETECT NC MONOINMONOIN+ LINEINR LINEINL MODE CSB SDIN SCLK TYPE Digital Input Supply Supply Supply Digital Input / Output Digital Input Digital Input / Output Digital Output Supply Analogue Output Analogue Output Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Supply Supply Analogue Output Analogue Output No Connect Logic Input No Connect Analogue Input Analogue Input Analogue Input Analogue Input Digital Input Digital Input Digital Input/Output Digital Input Master Clock Digital Core Supply Digital Buffer (I/O) Supply DESCRIPTION
Production Data
Digital Ground (return path for both DCVDD and DBVDD) Audio Interface Bit Clock DAC Digital Audio Data Audio Interface Left / Right Clock Buffered Clock Output (from MCLK or internal PLL) Internally connected to AGND. Connect this pin to AGND externally for best PLL performance, or leave floating. Mono Output Output 3 (can be used as Headphone Pseudo Ground) Right Output 1 (Line or Headphone) Left Output 1 (Line or Headphone) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2) Right Output 1 (Line or Headphone or Speaker) Left Output 1 (Line or Headphone or Speaker) Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT) Analogue Supply Analogue Ground (return path for AVDD) Reference Voltage Decoupling Capacitor Midrail Voltage Decoupling Capacitor No Internal Connection Headphone / Speaker switch (referred to AVDD) No Internal Connection Negative end of MONOIN+, for differential mono signals Analogue Line-in to mixers (mono channel) Analogue Line-in to mixers (right channel) Analogue Line-in to mixers (left channel) Control Interface Selection Chip Select / Device Address Selection Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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WM8955L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Supply voltages Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Notes 1. 2. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. MIN -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +4.5V DBVDD +0.3V AVDD +0.3V +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Ground SYMBOL DCVDD DBVDD AVDD, HPVDD DGND, AGND, HPGND TEST CONDITIONS MIN 1.42 1.71 1.8 0 TYP MAX 3.6 3.6 3.6 UNIT V V V V
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WM8955L ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Channel Separation Full-scale Input Signal Level Signal to Noise Ratio Line-in to Line-Out (A-weighted) Total Harmonic Distortion Input Resistance (signal enters one mixer only) Input Resistance (signal enters two mixers) MONOIN- input resistance Mute Attenuation Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT) 0dB Full scale output voltage Mute attenuation Channel Separation Headphone Output (LOUT1/2, ROUT1/2 with 16 or 32 load) Output Power per channel Total Harmonic Distortion PO THD Output power is very closely correlated with THD; see below. HPVDD=1.8V, RL=32 PO=5mW HPVDD=1.8V, RL=16 PO=5mW HPVDD=3.3V, RL=32, PO=20mW HPVDD=3.3V, RL=16, PO=20mW Signal to Noise Ratio (A-weighted) Output Power Total Harmonic Distortion SNR HPVDD = 3.3V HPVDD = 1.8V PO THD 92 0.018 -75 0.025 -72 0.013 -78 0.011 -79 96 95 dB dB % dB 1kHz, full scale signal AVDD/3.3 -94 -91 Vrms dB dB RMONOINVINFS SNR SYMBOL SNR THD TEST CONDITIONS AVDD = 3.3V AVDD = 1.8V AVDD = 3.3V AVDD = 1.8V 1kHz signal AVDD = 3.3V AVDD = other AVDD = 3.3V AVDD = 1.8V THD RLINEIN AVDD = 3.3V AVDD = 1.8V PGA gain = 0dB PGA gain = +6dB PGA gain = 0dB PGA gain = +6dB any gain Analogue Mixer Inputs (LINEINL/R to L/ROUT1 with 10k / 50pF load) 1.0 AVDD/3.3 98 95 -94 -90 20.5 10.5 10.25 5.25 20 -91 k dB dB dB k dB V rms MIN TYP 98 95 -86 -82 100 dB dB MAX UNIT dB DAC to Line-Out (L/ROUT1 with 10k / 50pF load)
Speaker Output (LOUT2/ROUT2 with 8 bridge tied load, ROUT2INV=1) Output power is very closely correlated with THD; see below and graphs Po=200mW, RL=8, HPVDD=3.3V Po=400mW, RL=8 HPVDD=3.3V Signal to Noise Ratio (A-weighted) SNR HPVDD=3.3V, RL=8 -63 0.07 -35 1.8 95 dB dB %
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WM8955L
Test Conditions DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Analogue Reference Levels Midrail Reference Voltage Buffered Reference Voltage Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level VIH VIL VOH VOL IOH = -1mA IOL = 1mA 0.9xDBVDD 0.1xDBVDD 0.7xDBVDD 0.3xDBVDD V V V V VMID VREF -3% -3% AVDD/2 AVDD/2 +3% +3% V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
3. 4.
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WM8955L
OUTPUT PGA'S LINEARITY
Production Data
10
0 Output PGA Gains -10 Measured Gain [db]
-20
-30 MONOOUT -40 ROUT1 LOUT1 ROUT2 LOUT2
-50
-60
-70 40 50 60 70 80 90 100 110 120 130
XXXVOL Register Setting [binary]
2
1.75 Output PGA Gain Step Size 1.5
Gain Step Size [dB]
1.25
1
0.75
0.5
0.25
MONOOUT ROUT1 LOUT1 ROUT2 LOUT2
0 40 50 60 70 80 90 100 110 120 130
XXXVOL Register Setting [binary]
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WM8955L
HEADPHONE OUTPUT THD VERSUS POWER
0
Headphone Power vs THD+N (16 Ohm load) -20
-40 THD+N [dB]
AVDD=3.3V AVDD=2.5V AVDD=1.8V -60
-80
-100 0 10 20 30 Power [mW] 40 50 60
0
Headphone Power vs THD+N (32 Ohm load)
-20
-40 THD+N [dB]
AVDD=3.3V AVDD=2.5V AVDD=1.8V -60
-80
-100 0 5 10 15 Power [mW] 20 25 30
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WM8955L
SPEAKER THD AND NOISE VERSUS POWER
Production Data
THD referenced to 0.95Vrms
WM8955 L/ROUT2 8R BTL Speaker Load THD+NvPo
AVDD=HPVDD=DBVDD=3.3V DCVDD=1.42V 1.013kHz sinewave input signal, A-weighted
0
-10
-20
THD+N (dB)
-30
-40
-50
-60
-70
-80
-90
-100 0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00 500.00
Output Power (mW)
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WM8955L
POWER CONSUMPTION
The power consumption of the WM8955L depends on the following factors. * Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings. * Operating mode: Power consumption is lower in mono modes than in stereo, as one DAC is switched OFF. Unused analogue outputs should be switched off.
Control Register
R25
R26 (1Ah)
R24 R23 R38
R43
Other settings
AVDD
DCVDD
DBVDD
HPVDD
Tot. Power
DACOSR
ROUT1
ROUT2
Bit
CLKOUTEN
VMIDSEL
LOUT1
LOUT2
PLLEN
MONO
DMEN
DACR
VREF
OUT3
DACL
VSEL
V Clocks stopped 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 R24, OUT3SW=00 3.3 2.5 1.8 R24, ROUT2INV=1 3.3 2.5 1.8 Clocks stopped 3.3 2.5 1.8 R24, ROUT2INV=1 Clocks stopped Clocks stopped 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 R24, ROUT2INV=1 3.3 2.5 1.8
I (mA) 0.0001 0.0001 0.0001 0.2339 0.1737 0.1208 3.9903 2.9459 2.0701 3.7821 2.7924 1.9604 3.9623 2.946 2.0702 4.0662 2.999 2.0705 3.9602 3.1282 2.1565 1.7135 1.211 0.8017 1.7132 1.2631 0.8881 1.9574 1.4258 0.9076 0.5389 0.4554 0.4034 0.5389 0.4554 0.4034 4.9869 3.737 2.6827
V 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5 3.3 2.5 1.5
I (mA) 0.0103 0.0084 0.0067 0.409 0.2556 0.1416 5.1104 3.5193 1.9742 4.2678 2.9224 1.6299 5.0846 3.5187 1.9742 5.1007 3.557 1.9164 4.2714 3.5487 1.9671 0.0901 0.009 0.0071 0.0905 0.009 0.0071 0.0905 0.009 0.0071 0.4966 0.2774 0.145 0.4953 0.2768 0.1448 5.1538 3.544 1.97
V 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8
I (mA) 0 0 0 0.0856 0.0616 0.042 0.0878 0.0632 0.0432 0.0879 0.0632 0.0432 0.0878 0.0632 0.04332 0.0881 0.064 0.04272 0.0873 0.0639 0.04296 0 0 0 0 0 0 0 0 0 0.0855 0.0616 0.04188 1.096 0.8044 0.57264 1.0972 0.8044 0.57348
V 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8 3.3 2.5 1.8
I (mA) 0 0 0 0 0 0 0.6621 0.6553 0.3845 0.6619 0.6557 0.3847 0.6913 0.6691 0.3852 1.172 1.167 0.914 0.8068 0.8039 0.6698 0.6624 0.6291 0.3869 1.158 1.0804 0.8733 1.1675 1.1017 0.6576 0 0 0 0 0 0 1.9463 1.7684 1.3114
(mW) 0.03432 0.02125 0.01023 2.40405 1.22725 0.50544 32.50698 17.95925 7.45734 29.03901 16.08425 6.74379 32.4258 17.9925 7.458996 34.4091 19.4675 8.8857 30.11481 18.86175 8.115318 8.1378 4.62275 2.15013 9.77361 5.88125 3.18117 10.61082 6.34125 2.82801 3.6993 1.986 1.019004 7.02966 3.8415 1.974072 43.50786 24.6345 11.176644
OFF
00
0
0
0
0
0
0
0
0
0
0
11 01 00
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Low-power standby (LPS) using 500 KOhm VMID string Playback to Line-out
10
1
0
0
0
0
0
0
0
0
0
11 01 00
01
1
1
1
0
0
1
1
0
0
0
11 01 00
Playback to Line-out (64x oversampling mode) Playback to 16 Ohm headphone using caps on HPOUTL/R Playback to 16 Ohm headphone capless mode using OUT3 Playback to 8 Ohm BTL speaker Headphone Amp line-in to 16 Ohm h/phone Speaker Amp line-in to 8 Ohm speaker Phone Call diff. mono line-in to h/phone, diff. mono line-out to TX PLL only
01
1
1
1
0
0
1
1
0
0
1
11 01 00
01
1
1
1
1
1
0
0
0
0
0
11 01 00
01
1
1
1
1
1
0
0
0
1
0
11 01 00
01
1
1
1
0
0
1
1
0
0
0
11 01 00
01
1
0
0
1
1
0
0
0
0
0
11 01 00
01
1
0
0
0
0
1
1
0
0
0
11 01 00
01
1
0
0
1
1
0
0
1
1
0
11 01 00
00
0
0
0
0
0
0
0
0
0
0
11 01 00
PLL and CLKOUT
00
0
0
0
0
0
0
0
0
0
0
11 01 00
Maximum Power everything ON
01
1
1
1
1
1
1
1
1
1
0
11 01 00
Table 1 Supply Current Consumption Notes: 1. 2. 3. TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), 24-bit data All figures are quiescent, with no signal. The power dissipated in the headphone itself is not included in the above table.
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WM8955L AUDIO PATHS OVERVIEW
Production Data
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WM8955L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2 = 0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK duty cycle TMCLKL TMCLKH TMCLKY TMCLKDS 21 21 54 60:40 40:60 ns ns ns SYMBOL MIN TYP MAX UNIT
Test Conditions CLKDIV2 = 1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time TMCLKL TMCLKH TMCLKY 10 10 27 ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
BCLK (Output) tDL DACLRC (Output) tDST DACDAT tDHT
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Bit Clock Timing Information BCLK rise time (10pF load) BCLK fall time (10pF load) BCLK duty cycle (normal mode, BCLK = MCLK/n) BCLK duty cycle (USB mode, BCLK = MCLK) tBCLKR tBCLKF tBCLKDS tBCLKDS 50:50 TMCLKDS 3 3 ns ns SYMBOL MIN TYP MAX UNIT
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WM8955L
Production Data
Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information DACLRC propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDST tDHT 10 10 10 ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
tBCH BCLK tBCY tBCL
DACLRC tDS DACDAT tLRH tLRSU
Figure 3 Digital Audio Data Timing - Slave Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low DACLRC setup time to BCLK rising edge DACLRC hold time from BCLK rising edge DACDAT hold time from BCLK rising edge tBCY tBCH tBCL tLRSU tLRH tDH 50 20 20 10 10 10 ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
CONTROL INTERFACE TIMING - 3-WIRE MODE
tCSL CSB tCSS tSCL tSCS tCSH
tSCY tSCH SCLK
SDIN tDSU tDHO
LSB
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode
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WM8955L
Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 500 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t8 t5 t3
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8955L INTERNAL POWER ON RESET CIRCUIT
DCVDD AVDD T1 VDD Power on Reset Circuit GND DGND
Figure 6 Internal Power on Reset Circuit Schematic
Production Data
Internal PORB
The WM8955 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state after power up. The power on reset circuit is powered from DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a minimum threshold.
Figure 7 Typical Power-Up Sequence Figure 7 shows a typical power-up sequence. When DCVDD and AVDD rise above the minimum thresholds, Vpord_dcvdd and Vpord_avdd, there is enough voltage for the circuit to guarantee the Power on Reset is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When DCVDD rises to Vpor_dcvdd_on and AVDD rises to Vpor_avdd_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. If DCVDD and AVDD rise at different rates then PORB will only be released when DCVDD and AVDD have both exceeded the Vpor_dcvdd_on and Vpor_avdd_on thresholds. On power down, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpor_dcvdd_off or AVDD drops below the minimum threshold Vpor_avdd_off.
SYMBOL Vpord_dcvdd Vpor_dcvdd_on Vpor_avdd_on Vpor_avdd_off
MIN 0.4 0.9 0.5 0.4
TYP 0.6 1.26 0.7 0.6
MAX 0.8 1.6 0.9 0.8
UNIT V V V V
Table 2 Typical POR Operation (typical values, not tested)
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WM8955L
DEVICE DESCRIPTION
INTRODUCTION
The WM8955L is a low power audio DAC offering a combination of high quality audio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications such as portable music players and smartphones. The device has a configurable digital audio interface where digital audio data is fed to the internal digital filters and then the DAC. The interface supports a number of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), Left Justified and Right Justified formats, and can operate in master or slave modes. The on-chip digital filters perform tone control and digital volume control according to the user setting, and convert the audio data into oversampled bitstreams, which are passed to the left and right channel DACs. A multi-bit, low-order DAC architecture with dynamic element matching is used, delivering optimum performance with low power consumption. The DAC output signal enters an analogue mixer where analogue input signals can be added to it. The WM8955L has a total of six analogue output pins, which can be configured as stereo line-outs, mono line-outs, differential mono line-outs, stereo headphone outputs or differential mono (BTL) speaker outputs. The WM8955L includes an on-chip PLL to generate commonly used audio rates, such as 48kHz and 44.1kHz, from system clocks found in GSM, CDMA and PDC phones and other portable systems. To allow full software control over all its features, the WM8955L offers a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The design of the WM8955L has given much attention to power consumption without compromising performance. It operates at very low voltages, and includes the ability to power off parts of the circuitry under software control, including standby and power off modes.
SIGNAL PATH
The WM8955L signal paths consists of digital filters, DACs, analogue mixers and output drivers. Each circuit block can be enabled or disabled separately using the control bits in register 26 (see "Power Management"). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8955L, irrespective of whether the DACs are running or not. The WM8955L receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: * * * * Digital volume control Tone control and Bass Boost Digital Mono Mix Sigma-Delta Modulation
Two high performance, sigma-delta audio DACs convert the digital data into two analogue signals (left and right). These can then be mixed with analogue signals from the LINEINL, LINEINR and MONOIN pins, and the mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2, MONOOUT and OUT3. * * * * LOUT1/ROUT1: can drive 16 or 32 stereo headphones or stereo line output. LOUT2/ROUT2: can drive an 8 mono speaker, stereo headphones or a stereo line-out. MONOOUT: line output designed to drive a 10k load. OUT3: multi-function output, may be used for capacitor-less headphone drive, differential mono-out, line-out or 32 earpiece driver.
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WM8955L
DIGITAL VOLUME CONTROL
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The WM8955L has on-chip digital attenuation from -127dB to 0dB in 0.5dB steps, allowing the user to adjust the volume of each channel separately. The level of attenuation for an eight-bit code X is given by: -0.5 x (255 - X) dB for 1 X 255; MUTE for X = 0
The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register, but the actual gain does not change. Both left and right gain settings are updated simultaneously when either LDVU or RDVU are set to 1.
REGISTER ADDRESS R10 (0Ah) Left Channel Digital Volume
BIT 7:0
LABEL LDACVOL[7:0]
DEFAULT 11111111 ( 0dB )
DESCRIPTION Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Left DAC Volume Update 0 = Store LDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LDACVOL, right = intermediate latch) Right DAC Digital Volume Control similar to LDACVOL Right DAC Volume Update 0 = Store RDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = RDACVOL)
8
LDVU
0
R11 (0Bh) Right Channel Digital Volume
7:0 8
RDACVOL[7:0] RDVU
11111111 ( 0dB ) 0
Table 3 Digital Volume Control
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WM8955L
TONE CONTROL
The WM8955L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: * Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear.
*
Treble control applies a user programmable gain, without any adaptive boost function. REGISTER ADDRESS R12 (0Ch) Bass Control BIT 7 LABEL BB 0 DEFAULT DESCRIPTION Bass Mode 0 = Linear bass control 1 = Adaptive bass boost Bass Filter Characteristic 0 = Low Cutoff (130 Hz at 48kHz sampling) 1 = High Cutoff (200 Hz at 48kHz sampling) Bass Intensity Code 0000 0001 0010 ... 0111 ... 1011-1101 1110 1111 R13 (0Dh) Treble Control 6 TC 0 BB=0 +9dB +9dB +7.5dB (1.5dB steps) 0dB (1.5dB steps) -6dB -6dB BB=1 15 (max) 14 13 ... 8 ... 4-2 1 (min) Bypass (OFF)
6
BC
0
3:0
BASS
1111 (OFF)
Treble Filter Characteristic 0 = High Cutoff (8kHz at 48kHz sampling) 1 = Low Cutoff (4kHz at 48kHz sampling) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB ... (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable
3:0
TRBL
1111 (Disabled)
Table 4 Tone Control Note: All cut-off frequencies change proportionally with the DAC sample rate.
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WM8955L
DIGITAL TO ANALOGUE CONVERTER (DAC)
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Treble and linear bass enhancement may produce signals that exceed full-scale. In order to avoid limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input signal by 6dB. The gain at the outputs should be increased by 6dB to compensate for the attenuation. Cut-only tone adjustment and adaptive bass boost cannot produce signals above fullscale and therefore do not require the DAT bit to be set. After passing through the tone control filters, digital `de-emphasis' can be applied to the audio data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording). Deemphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8955L also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. This function is enabled by default. To play back an audio signal, the WM8955L must first be unmuted by setting the DACMU bit to zero. REGISTER ADDRESS R5 (05h) DAC Control BIT 7 LABEL DAT DEFAULT 0 DESCRIPTION DAC 6dB attenuate enable 0 = disabled (0dB) 1 = -6dB enabled Digital Soft Mute 1 = mute 0 = no mute (signal active) De-emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No De-emphasis
3
DACMU
1
2:1
DEEMPH
00
Table 5 DAC Control The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. In normal operation, the left and right channel digital audio data are converted to analogue in two separate DACs. However, it is also possible to disable one channel, so that the same signal (left or right) appears on both analogue output channels. Additionally, there is a mono-mix mode where the two audio channels are mixed together digitally and then converted to analogue using only one DAC, while the other DAC is switched off. The mono-mix signal can be selected to appear on both analogue output channels (see Analogue Outputs). The DAC output defaults to non-inverted. Setting DACINV will invert the DAC output phase on both left and right channels. REGISTER ADDRESS R23 (17h) Additional (1) BIT 5:4 LABEL DMONOMIX[1:0] DEFAULT 00 DESCRIPTION DAC mono mix 00: stereo 01: mono ((L+R)/2) into DACL, `0' into DACR 10: mono ((L+R)/2) into DACR, `0' into DACL 11: mono ((L+R)/2) into DACL & DACR DAC phase invert 0: non-inverted 1: inverted
1
DACINV
0
Table 6 DAC Mono Mix Select
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WM8955L
LINE INPUTS AND OUTPUT MIXERS
The WM8955L provides the option to mix the DAC output signal with analogue line-in signals from the LINEINL, LINEINR and MONOIN+ and MONOIN- pins. The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers). LINEINL, LINEINR, MONOIN+ and MONOIN- are high impedance, low capacitance AC coupled analogue inputs. They are biased internally to the reference voltage VREF. Whenever these inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs. The mono mixer is designed to allow a number of signal combinations to be mixed, including the possibility of mixing both the right and left channels together to produce a mono output. To prevent overloading of the mixer when full-scale DAC left and right signals are input, the mixer inputs from the DAC outputs each have a fixed gain of -6dB. The bypass path inputs to the mono mixer have variable gain as determined by R38/R39 bits [6:4].
REGISTER ADDRESS R34 (22h) Left Mixer (1)
BIT 8
LABEL LD2LO 0
DEFAULT
DESCRIPTION Left DAC to Left Mixer 0 = Disable (Mute) 1 = Enable Path LINEINL Signal to Left Mixer 0 = Disable (Mute) 1 = Enable Path LINEINL Signal to Left Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Right DAC to Left Mixer 0 = Disable (Mute) 1 = Enable Path MONOIN Signal to Left Mixer 0 = Disable (Mute) 1 = Enable Path MONOIN Signal to Left Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB
7
LI2LO
0
6:4
LI2LOVOL
101 (-9dB)
R35 (23h) Left Mixer (2)
8
RD2LO
0
7
MI2LO
0
6:4
MI2LOVOL
101 (-9dB)
Table 7 Left Output Mixer Control
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WM8955L
REGISTER ADDRESS R36 (24h) Right Mixer (1) BIT 8 LABEL LD2RO 0 DEFAULT
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DESCRIPTION Left DAC to Right Mixer 0 = Disable (Mute) 1 = Enable Path MONOIN Signal to Right Mixer 0 = Disable (Mute) 1 = Enable Path MONOIN Signal to Right Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Right DAC to Right Mixer 0 = Disable (Mute) 1 = Enable Path LINEINR Signal to Right Mixer 0 = Disable (Mute) 1 = Enable Path LINEINR Signal to Right Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB
7
MI2RO
0
6:4
MI2ROVOL
101 (-9dB)
R37 (25h) Right Mixer (2)
8
RD2RO
0
7
RI2RO
0
6:4
RI2ROVOL
101 (-9dB)
Table 8 Right Output Mixer Control
REGISTER ADDRESS R38 (26h) Mono Mixer (1)
BIT 8
LABEL LD2MO 0
DEFAULT
DESCRIPTION Left DAC to Mono Mixer 0 = Disable (Mute) 1 = Enable Path LINEINL Signal to Mono Mixer 0 = Disable (Mute) 1 = Enable Path LINEINL Signal to Right Mono Volume 000 = 0dB ... (3dB steps) 111 = -21dB Right DAC to Mono Mixer 0 = Disable (Mute) 1 = Enable Path LINEINR Signal to Mono Mixer 0 = Disable (Mute) 1 = Enable Path LINEINR Signal to Mono Mixer Volume 000 = 0dB ... (3dB steps) 111 = -21dB
7
LI2MO
0
6:4
LI2MOVOL
101 (-9dB)
R39 (27h) Mono Mixer (2)
8
RD2MO
0
7
RI2MO
0
6:4
RI2MOVOL
101 (-9dB)
Table 9 Mono Output Mixer Control Note: The mono mixer has half the gain of the left and right mixers (i.e. 6dB less), to ensure that the left and right channels can be mixed to mono without clipping.
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WM8955L
DIFFERENTIAL MONO LINE-IN
The WM8955L can take either a single-ended or a differential mono signal and mix it into the LOUT1/2 and ROUT1/2 outputs. In both cases, LINEINL and LINEINR still remain available as stereo line-in. Differential mono input mode is enabled by setting the DMEN bit, as shown below. REGISTER ADDRESS R38 (26h) Mono Mixer (1) BIT 0 LABEL DMEN 0 DEFAULT DESCRIPTION Differential mono line-in enable 0 = Single-ended line-in from MONOIN+ 1 = Differential line-in
Table 10 Differential Mono Line-in Enable
DEVICE WITH DIFFERENTIAL MONO OUTPUT
MONO OUT(-) MONO OUT(+)
MONOIN+
MONOIN-
DMEN = 1 (ON)
LEFT LD2LO MIXER
DIFF. IN
LI2LO
LINEINL LINEINR
LOUT1
RD2LO
DAC
LD2MO VREF MONO MIXER
MI2LO LI2MO
LOUT1VOL
MONOOUT
RD2MO RI2MO MI2RO MONOVOL
DAC
RIGHT LD2RO MIXER
ROUT1
RD2RO RI2RO ROUT1VOL
LOUT2
LOUT2VOL ROUT2 INV
W
WM8955L
-1
Loudspeaker L - (-R) = L+R ROUT2
ROUT2VOL
Figure 8 Differential Mono Line-in Configuration (DMEN=1)
DEVICE WITH SINGLE-ENDED MONO OUTPUT
MONO OUT
MONOIN- (connect to VREF)
MONOIN+
DMEN = 0 (OFF)
LEFT LD2LO MIXER
DIFF. IN
LI2LO
LINEINL LINEINR
LOUT1
RD2LO
DAC
LD2MO VREF MONO MIXER
MI2LO LI2MO
LOUT1VOL
MONOOUT
RD2MO RI2MO MI2RO MONOVOL
DAC
RIGHT LD2RO MIXER
ROUT1
RD2RO RI2RO ROUT1VOL
LOUT2
LOUT2VOL ROUT2 INV
W
WM8955L
-1
Loudspeaker L - (-R) = L+R ROUT2
ROUT2VOL
Figure 9 Single-ended Mono Line-in Configuration (DMEN=0)
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WM8955L
ANALOGUE OUTPUTS
ENABLING THE OUTPUTS
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Each analogue output of the WM8955L can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To save power, unused outputs should remain disabled. Outputs can be enabled at any time, except when the WM8955L is in OFF mode, as this may cause pop noise (see Minimising Pop Noise at the Analogue Outputs) REGISTER ADDRESS R26 (1Ah) Power Management (2) BIT 6 5 4 3 2 1 LABEL LOUT1 ROUT1 LOUT2 ROUT2 MONO OUT3 0 0 0 0 0 0 DEFAULT DESCRIPTION 0 = LOUT1 disabled 1 = LOUT1 enabled 0 = ROUT1 disabled 1 = ROUT1 enabled 0 = LOUT2 disabled 1 = LOUT2 enabled 0 = ROUT2 disabled 1 = ROUT2 enabled 0 = MONOOUT disabled 1 = MONOOUT enabled 0 = OUT3 disabled 1 = OUT3 enabled
Table 11 Analogue Output Control Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and each output can be controlled using the VROI bit in register 27. The default is low (1.5k), so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 40k. REGISTER ADDRESS R27 (1Bh) Additional (3) BIT 6 LABEL VROI 0 DEFAULT DESCRIPTION VREF to analogue output resistance 0: 1.5 k 1: 40 k
Table 12 Disabled Outputs to VREF Resistance
THERMAL SHUTDOWN
The speaker and headphone outputs can drive very large currents. To protect the WM8955L from overheating, a thermal shutdown circuit is included. If the device temperature reaches approximately 1500C and the thermal shutdown circuit is enabled (TSDEN = 1 ) then the speaker and headphone amplifiers (outputs OUT1L/R, OUT2L/R & OUT3) will be disabled. REGISTER ADDRESS R23 (17h) Additional (1) BIT 8 LABEL TSDEN 0 DEFAULT DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 13 Thermal Shutdown
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WM8955L
HEADPHONE SWITCH
The HPDETECT pin can be used as a headphone switch control input to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. In this mode, enabled by setting HPSWEN, HPDETECT switches between headphone and speaker outputs (typically, the pin is connected to a mechanical switch in the headphone socket to detect plug-in). The HPSWPOL bit reverses the pin's polarity. HPDETECT has CMOS thresholds at 0.3 AVDD / 0.7 AVDD. Note that the LOUT1, ROUT1, LOUT2 and ROUT2 bits in register 26 must also be set to enable headphone and speaker outputs (see tables below). REGISTER ADDRESS R24 (18h) Additional (1) BIT 6 LABEL HPSWEN 0 DEFAULT DESCRIPTION Headphone Switch Enable 0 : Headphone switch disabled 1 : Headphone switch enabled Headphone Switch Polarity 0 : HPDETECT high = headphone 1 : HPDETECT high = speaker Headphone Switch Zero Cross Enable 0 : Switch immediately 1 : Switch on zero crossing only
5
HPSWPOL
0
3
HPSWZC
0
Table 14 Headphone Switch HPSWEN 0 0 0 0 1 1 1 1 1 1 1 1 HPSWPOL HPDETECT (PIN23) X X X X 0 0 0 0 1 1 1 1 X X X X 0 0 1 1 0 0 1 1 L/ROUT1 (reg. 26) 0 0 1 1 X X 0 1 0 1 X X L/ROUT2 (reg. 26) 0 1 0 1 0 1 X X X X 0 1 Headphone enabled no no yes yes no no no yes no yes no no Speaker enabled no yes no yes no yes no no no no no yes
Table 15 Headphone Switch Operation
Figure 10 Example Headset Detection Circuit Using Normally-Open Switch
HPSWEN = 1 HPSWPOL = 0 L/ROUT1 = L/ROUT2 = 1 headphone / speaker switching
AVDD ROUT1 LOUT1 33k HPDETECT switch opens on insertion
L R
Figure 11 Example Headset Detection Circuit Using Normally-Closed Switch
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WM8955L
LOUT1/ROUT1 OUTPUTS
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The LOUT1 and ROUT1 pins can drive a 16 or 32 headphone or a line output (see Headphone Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting below 0101111 (minimum gain) mutes the output driver. The corresponding output pin remains at the same DC level (the reference voltage on the VREF pin), so that no click noise is produced when muting or un-muting. The analogue outputs have a zero cross detect feature to minimize audible clicks and zipper noise when on gain changes (i.e. the updating of the gain value is delayed until the signal passes through zero). By default, this includes a time-out function, which forces the gain to update if no zero crossing occurs within a certain period of time.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R2 (02h) LOUT1 Volume
6:0
LOUT1VOL
1111001 (0dB)
LOUT1 Volume 1111111 = +6dB ... (80 steps) 0110000 = -67dB 0101111 to 0000000 = Analogue MUTE LOUT1 zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately Left Volume Update 0 = Store LOUT1VOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LOUT1VOL, right = intermediate latch) ROUT1 Volume Similar to LOUT1VOL ROUT1 zero cross enable Similar to LO1ZC Right Volume Update 0 = Store ROUT1VOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = ROUT1VOL) Time-out enable for zero-cross detectors 0 = time-out disabled (i.e. gains are never updated if there is no zero crossing) 1 = time-out enabled
7
LO1ZC
0
8
LO1VU
0
R3 (03h) ROUT1 Volume
6:0 7 8
ROUT1VOL RO1ZC RO1VU
1111001 (0dB) 0 0
R23 (17h)
0
TOEN
1
Table 16 LOUT1/ROUT1 Volume Control
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WM8955L
LOUT2/ROUT2 OUTPUTS
The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled and can drive an 8 mono speaker. For speaker drive, the ROUT2 signal must be inverted (ROUT2INV = 1), so that the left and right channel are mixed to mono in the speaker [L-(-R) = L+R].
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R40 (28h) LOUT2 Volume
6:0 7
LOUT2VOL LO2ZC
1111001 (0dB) 0
similar to LOUT1VOL Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately similar to LO1VU similar to ROUT1VOL Right zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately similar to RO1VU as for LOUT1 / ROUT1 ROUT2 Invert 0 = No Inversion (0 phase shift) 1 = Signal inverted (180 phase shift)
8 R41 (29h) ROUT2 Volume 6:0 7
LO2VU ROUT2VOL RO2ZC
0 1111001 (0dB) 0
8 R23 (17h) R24 (18h) Additional (2) 0 4
RO2VU TOEN ROUT2INV
0 1 0
Table 17 LOUT2/ROUT2 Control
MONO OUTPUT
The MONOOUT pin can drive a mono line output. The signal volume on MONOOUT can be adjusted under software control by writing to MONOOUTVOL.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R42 (2Ah) MONOOUT Volume
6:0
MONOOUT VOL
1111001 (0dB)
MONOOUT Volume 1111111 = +6dB ... (80 steps) 0110000 = -67dB 0101111 to 0000000 = Analogue MUTE MONOOUT zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately as for LOUT1 / ROUT1
7
MOZC
0
R23 (17h)
0
TOEN
1
Table 18 MONOOUT Volume Control
OUT3 OUTPUT
The OUT3 pin can drive a 16 or 32 headphone or a line output or be used as a DC reference for a headphone output. It can be selected to either drive out an inverted ROUT1 or inverted MONOOUT for e.g. an earpiece drive between OUT3 and LOUT1 or differential output between OUT3 and MONOOUT. OUT3SW selects the mode of operation required.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R24 (18h) Additional (2)
8:7
OUT3SW
00
OUT3 select 00 : VREF 01 : ROUT1 10 : MONOOUT 11 : right mixer output
Table 19 OUT3 Select
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DIGITAL AUDIO INTERFACE
Production Data
The digital audio interface is used for feeding audio data into the WM8955L. It uses three pins:
* * *
DACDAT: DAC data input DACLRC: DAC data alignment clock BCLK: Bit clock, for synchronisation
The clock signals BCLK and DACLRC can be outputs when the WM8955L operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported:
* * * *
Left justified Right justified I 2S DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8955L can be configured as either a master or slave mode device. As a master device the WM8955L generates BCLK and DACLRC and thus controls sequencing of the data transfer on DACDAT. In slave mode, the WM8955L responds with data to clocks it receives over the digital audio interface. The mode can be selected by writing to the MS control bit. Master and slave modes are illustrated below.
BCLK WM8955L DAC DACLRC DACDAT DSP / DECODER
WM8955L DAC
BCLK DACLRC DACDAT DSP / DECODER
Figure 12 Master Mode
Figure 13 Slave Mode
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a DACLRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each DACLRC transition.
Figure 14 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a DACLRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each DACLRC transition.
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WM8955L
Figure 15 Right Justified Audio Interface (assuming n-bit word length)
In I S mode, the MSB is available on the second rising edge of BCLK following a DACLRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
2
Figure 16 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the first or second rising edge of BCLK (selectable by LRP) following a rising edge of DACLRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 17 DSP Mode Audio Interface (Mode A; LRP = 0)
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Figure 18 DSP Mode Audio Interface (Mode B; LRP = 1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R7 (07h) Digital Audio Interface Format
1:0
FORMAT
10
Audio Data Format Select 11 = DSP Mode 10 = I2S Format 01 = Left justified 00 = Right justified Audio Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits I2S, LJ, RJ Formats 1: Invert LRCLK polarity 0: Normal LRCLK polarity DSP Format 1: MSB available on st 1 BCLK rising edge after LRC rising edge 0: MSB available on 2nd BCLK rising edge after LRC rising edge
3:2
WL
10
4
LRP
0
5
LRSWAP
0
Swap Left and Right Channels 0: No swap (L to L, R to R) 1: Swap (L to R, R to L) Master / Slave Mode Control 1: Master Mode 0: Slave Mode BCLK Invert 1: BCLK inverted 0: BCLK not inverted
6
MS
0
7
BCLKINV
0
Table 20 Audio Data Format Control Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual word length will be 24 bits.
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WM8955L
MASTER CLOCK AND PHASE LOCKED LOOP
The WM8955L has an on-chip phase-locked loop (PLL) circuit that can be used to:
* *
generate a master clock for the WM9755L audio function from another external clock, e.g. in telecoms applications. generate a clock for another part of the system from an existing audio master clock.
The PLL circuit is shown below.
MCLK DIV2 MCLK PLL f/2 f/4 R = f2 / f1 f/2
PLLOUT DIV2
MCLK SEL DIGITAL CORE
f1
CLKOUTEN CLKOUT CLKOUT DIV2
f2
CLKOUT SEL
f/2
Figure 19 PLL Circuit REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R8 (08h) Sample Rates
8
CLKOUTDIV2
0
CLKOUT Divide by 2 0: Divide disabled 1: Divide enabled MCLK Divide by 2 0: Divide disabled 1: Divide enabled Select internal master clock 0: from MCLK pin 1: from PLL (make sure PLLEN=1) CLKOUT Enable 0: Pin disabled (tri-state) 1: Pin Enabled Select source of CLKOUT 0: from MCLK pin 1: from PLL (make sure PLLEN=1) PLL Output Divide by 2 0: Divide disabled 1: Divide enabled 0: PLL held in reset 1: PLL running (if PLLEN=1) PLL Enable 0: PLL disabled; 1: PLL enabled.
6
MCLKDIV2
0
R43 (2Bh) Clocking and PLL
8
MCLKSEL
0
7
CLKOUTEN
0
6
CLKOUTSEL
0
5
PLLOUTDIV2
0
4 3
PLL_RB PLLEN
0 0
Table 21 PLL and Clocking Control
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Production Data The PLL frequency ratio R = f2/f1 (see Figure 19) can be set using K and N in registers 44 (2Ch) to 46 (2Eh): N = int (R) K = int (222 (R-N)) Example: MCLK = 12MHz required clock = 12.288MHz R should be chosen to ensure 5REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R44 (2Ch) PLL Control (1)
8:5
N
1000
Integer part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional part of PLL input/output frequency ratio (treat as one 22-digit binary number)
3:0 R45 (2Dh) PLL Control (2) R46 (2Eh) PLL Control (3) R59 (3Bh) 8:0 8:0 7
K [21:18] K [17:9] K [8:0] KEN
0011 024h 1BAh 0
0: Fractional part (K) disabled 1: K enabled
Table 22 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown below.
MCLK (MHz) DESIRED OUTPUT (MHz) F2 (MHz) MCLK DIV2 PLL OUT DIV2 CLK OUT DIV2 R F2 (Hex) K (Hex)
11.91 11.91 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27
11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288
90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.5833 8.2539 7.5264 8.192 6.9474 7.5618 6.272 6.8267 9.408 10.24 9.1785 9.9902 9.1229 9.9297 7.5264 8.192 6.9474 7.5618 6.6901 7.2818
7 8 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7
25545C 103FF6 21B089 C49BA 3CA2F4 23F548 116872 34E818 1A1CAC F5C28 B6D22 3F6017 7DDCA 3B8023 21B089 C49BA 3CA2F4 23F548 2C2B30 12089E
Table 23 PLL Frequency Examples
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WM8955L
The WM8955L supports a wide range of master clock frequencies and can generate many commonly used audio sample rates directly from the master clock. There are two clocking modes:
* *
AUDIO SAMPLE RATES
`Normal' mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in systems with a USB interface, and can run without a PLL.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h) Sample Rates
0
USB
0
Clocking Mode Select 1: USB Mode 0: `Normal' Mode Sample Rate Control MCLK Divide by 2 0: Divide disabled 1: Divide enabled Divide BITCLK output by 2 (use only in USB master mode, i.e. when USB=1, MS=1) 1 = BCLK is divided by 2 (Note 1) 0 = BCLK is not divided MCLK Divide by 2 0: Divide disabled 1: Divide enabled
5:1 6
SR [4:0] MCLK DIV2
00000 0
7
BCLKDIV2
0
8
CLKOUT DIV2
0
Table 24 Clocking and Sample Rate Control Note:
1.
With BCLKDIV2=1, the LRCLK output produces a non-50:50 duty cycle if BCLK/LRCLK is not an even integer.
The clocking of the WM8955L is controlled using the MCLKDIV2, USB, and SR control bits. Setting the MCLKDIV2 bit divides MCLK by two internally. The USB bit selects between `Normal' and USB mode. Each combination of the SR4 to SR0 control bits selects one MCLK division ratio and hence one sample rate (see Table 25). The digital filter characteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital Filter Characteristics). Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small amount. This is not audible, as the maximum deviation is only 0.27% (8.0214kHz instead of 8kHz in USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).
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MCLK MCLKDIV2=0 MCLK MCLKDIV2=1 DAC SAMPLE RATE USB SR [4:0] FILTER TYPE
Production Data
BCLK (MS=1)
`Normal' Clock Mode (`*' indicates backward compatibility with WM8711 and WM8721)
12.288MHz
24.576MHz
8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 96 kHz (MCLK/128)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
00010 * 01000 01010 11100 01100 * 00000 * 01110 * 10010 11000 11010 10000 * 11110 * 00011 * 01001 01011 11101 01101 * 00001 * 01111 * 10011 * 11001 11011 10001 * 11111 * 00010 * 11001 01000 01010 11011 11100 01100 * 10001 * 00000 * 11111 * 01110 *
1 1 1 1 1 1 3 1 1 1 1 3 1 1 1 1 1 1 3 1 1 1 1 3 0 1 0 0 1 0 0 1 0 3 2
MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/3 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/3 MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK
11.2896MHz
22.5792MHz
8.0182 kHz (MCLK/1408) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 44.1 kHz (MCLK/256) 88.2 kHz (MCLK/128)
18.432MHz
36.864MHz
8 kHz (MCLK/2304) 12 kHz (MCLK/1536) 16 kHz (MCLK/1152) 24 kHz (MCLK/768) 32 kHz (MCLK/576) 48 kHz (MCLK/384) 96 kHz (MCLK/192)
16.9344MHz
33.8688MHz
8.0182 kHz (MCLK/2112) 11.025 kHz (MCLK/1536) 22.05 kHz (MCLK/768) 44.1 kHz (MCLK/384) 88.2 kHz (MCLK/192)
USB Mode (assumes BCLKDIV2=0. `*' indicates backward compatibility with WM8711 and WM8721)
12.000MHz
24.000MHz
8 kHz (MCLK/1500) 11.0259 kHz (MCLK/1088) 12kHz (MCLK/1000) 16kHz (MCLK/750) 22.0588 kHz (MCLK/544) 24kHz (MCLK/500) 32 kHz (MCLK/375) 44.118 kHz (MCLK/272) 48 kHz (MCLK/250) 88.235kHz (MCLK/136) 96 kHz (MCLK/125)
Table 25 Master Clock and Sample Rates
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WM8955L
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8955L is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin selects the interface format.
MODE INTERFACE FORMAT
Low High
2 wire 3 wire
Table 26 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB latches in a complete control word consisting of the last 16 bits.
latch CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 20 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8955L supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8955L). The WM8955L operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8955L and the R/W bit is `0', indicating a write, then the WM8955L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1', the WM8955L returns to the idle condition and wait for a new start condition and valid address. Once the WM8955L has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8955L register address plus the first bit of register data). The WM8955L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8955L acknowledges again by pulling SDIN low. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high. After receiving a complete address and data sequence the WM8955L returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
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Figure 21 2-Wire Serial Control Interface
The WM8955L has two possible device addresses, which can be selected using the CSB pin.
CSB STATE DEVICE ADDRESS
Low High
0011010 0011011
Table 27 2-Wire MPU Interface Address Selection
POWER SUPPLIES
The WM8955L can use up to four separate power supplies:
*
*
*
*
AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers. AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A large AVDD slightly improves audio quality. HPVDD / HPGND: Headphone supply, powers the headphone drivers. HPVDD is normally tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. If HPVDD is lower than AVDD, the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it possible to run the digital core at very low voltages, saving power, while interfacing to other digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has no effect on audio quality. The return path for DBVDD is DGND, which is shared with DCVDD.
It is possible to use the same supply voltage on all four. However, digital and analogue supplies should be routed and decoupled separately to keep digital switching noise out of the analogue signal paths.
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WM8955L
POWER MANAGEMENT
The WM8955L has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise, it is important to enable or disable functions in the correct order (see Applications Information)
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R25 (19h) Power Manageme nt (1)
8:7
VMIDSEL
00
VMID resistor divider select 00 - VMID disabled 01 - 50k divider enabled 10 - 500k divider enabled 11 - 5k divider enabled (for fast start-up) VREF (necessary for all other functions) DAC Left Enable 0=off 1=on DAC Right Enable 0=off 1=on LOUT1 Output Buffer* Enable 0=off 1=on ROUT1 Output Buffer* Enable 0=off 1=on LOUT2 Output Buffer* Enable 0=off 1=on ROUT2 Output Buffer* Enable 0=off 1=on MONOOUT Output Buffer and Mono Mixer Enable 0=off 1=on OUT3 Output Buffer Enable 0=off 1=on
6 R26 (1Ah) Power Manageme nt (2) 8
VREF DACL
0 0
7
DACR
0
6
LOUT1
0
5
ROUT1
0
4
LOUT2
0
3
ROUT2
0
2
MOUT
0
1
OUT3
0
Note: * The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when ROUT1=1 or ROUT2=1. Table 28 Power Management
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STOPPING THE MASTER CLOCK
Production Data
In order to minimise power consumed in the digital core of the WM8955L, the master clock should be stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. However, since setting DIGENB has no effect on the power consumption of other system components external to the WM8955L, it is preferable to disable the master clock at its source wherever possible.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R25 (19h) Additional Control (1)
0
DIGENB
0
Master clock disable 0: master clock enabled 1: master clock disabled
Table 29 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits DACL and DACR must be set to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs and ADCs from re-starting correctly.
OVERSAMPLING RATE
By default, the oversampling rate of the DAC digital filters is 128x. However, this can be changed to 64x by writing to the DACOSR bit. In the 64x oversampling mode, the digital filters consumes less power. However, the signal-to-noise ratio is slightly reduced.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
0
DACOSR
0
DAC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR)
Table 30 Oversampling Rate Selection
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM8955L can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below.
REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION
R23 (17h) Additional Control(1)
7:6
VSEL[1:0]
11
Analogue Bias optimization 00 : Lowest bias current, optimized for 1.8V 01 : Low bias current, optimized for 2.5V 10, 11 : Default bias current, optimized for 3.3V
Table 31 Analogue Bias Selection
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WM8955L
REGISTER MAP
REGISTER R0 (00h) R1 (01h) R2 (02h) R3 (03h) R4 (04h) R5 (05h) R6 (06h) R7 (07h) R8 (08h) ADDRESS (BIT 15 - 9) 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 REMARKS Reserved Reserved LOUT1 ROUT1 Reserved DAC Control Reserved Audio Interface Sample Rates 0 CLKOUT DIV2 R9 (09h) R10 (0Ah) R11 (0Bh) R12 (0Ch) R13 (0Dh) R14 (0Eh) R15 (0Fh) R16 - R22 R23 (17h) R24 (18h) R25 (19h) R26 (1Ah) R27 (1Bh) R28 - R33 R34 (22h) R35 (23h) R36 (24h) R37 (25h) R38 (26h) R39 (27h) R40 (28h) R41 (29h) R42 (2Ah) R43 (2Bh) 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 Left Mix (1) Left Mix (2) Right Mix (1) Right Mix (2) Mono Mix (1) Mono Mix (2) LOUT2 ROUT2 MONOOUT Clocking / PLL LD2LO RD2LO LD2RO RD2RO LD2MO RD2MO LO2VU RO2VU 0 MCLKSEL LI2LO MI2LO MI2RO RI2RO LI2MO RI2MO LO2ZC RO2ZC MOZC CLKOUT EN R44 (2Ch) R45 (2Dh) R46 (2Eh) R59 (3Bh) 0101110 0111011 PLL Control (3) PLL Control (4) 0 KEN 0 0 K [8:0] 0 0 0 0 0 0101101 PLL Control (2) K [17:9] 0101100 PLL Control (1) N CLKOUT SEL PLLOUT DIV2 0 K [21:18] PLL_RB LI2LOVOL MI2LOVOL MI2ROVOL RI2ROVOL LI2MOVOL RI2MOVOL 0 0 0 0 0 0 LOUT2VOL ROUT2VOL MONOOUTVOL PLLEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMEN 0 0010111 0011000 0011001 0011010 0011011 Additional (1) Additional (2) Pwr Mgmt (1) Pwr Mgmt (2) Additional (3) Reserved TSDEN OUT3SW VMIDSEL DACL 0 DACR 0 VSEL HPSWEN VREF LOUT1 VROI DMONOMIX HPSWPOL ROUT2INV 0 ROUT1 0 0 LOUT2 0 0 HPSWZC 0 ROUT2 0 0 0 0 MOUT 0 DACINV 0 0 OUT3 0 TOEN DACOSR DIGENB 0 0 0001110 0001111 TBD Reset Reserved 000000000 writing 000000000 to this register resets all registers to their default state 000000 0001101 Treble 0 0 TC 0 0 TRBL (Treble Intensity) 0001001 0001010 0001011 0001100 Reserved Left Gain Right Gain Bass LDVU RDVU 0 BB BC BCLKINV BCLK DIV2 MS MCLK DIV2 000000000 LDACVOL (Right DAC Digital Volume) RDACVOL (Right DAC Digital Volume) 0 0 BASS (Bass Intensity) LRSWAP 0 DAT 0 0 LO1VU RO1VU LO1ZC RO1ZC 000000000 0 000000000 LRP SR WL FORMAT USB DACMU DEEMPH 0 BIT8 BIT7 BIT6 BIT5 BIT4 000000000 000000000 LOUT1VOL ROUT1VOL BIT3 BIT2 BIT1 BIT0
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WM8955L DIGITAL FILTER CHARACTERISTICS
Production Data
Depending on the MCLK frequency and sample rate selected, 4 different types of digital filter can be used in the DAC, called Type 0, 1, 2 and 3 (see "Master Clock and Audio Sample Rates"). The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the following pages.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC Filter Type 0 (USB mode, 250fs operation)
Passband Passband Ripple Stopband Stopband Attenuation Passband Passband Ripple Stopband Stopband Attenuation
Table 32 Digital Filter Characteristics MODE
+/- 0.03dB -6dB
0 0.5fs
0.416fs +/-0.03 dB dB 0.4535fs 0.5fs +/- 0.03 dB dB
0.584fs f > 0.584fs +/- 0.03dB -6dB 0.5465fs f > 0.5465fs -50 -50 0
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
GROUP DELAY
0 (250 USB) 1 (256/272) 2 (250 USB, 96k mode) 3 (256/272, 88.2/96k mode)
Table 33 DAC Filters
11/FS 16/FS 4/FS 3/FS
TERMINOLOGY
Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
DAC FILTER RESPONSES
0.02
0
0.01
-20
0
Response (dB)
-40
Response (dB)
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.01 -0.02 -0.03 -0.04 -0.05
-60
-80
-100
-0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 22 DAC Filter Frequency Response - Type 0
Figure 23 DAC Filter Ripple - Type 0
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0.02
WM8955L
0.01
0
-20
0
Response (dB)
-40
Response (dB)
-0.01 -0.02 -0.03 -0.04
-60
-80
-0.05
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 24 DAC Filter Frequency Response - Type 1
0
Figure 25 DAC Filter Ripple - Type 1
0.02 0.01
-20
0
Response (dB)
-40
Response (dB)
-0.01 -0.02 -0.03 -0.04
-60
-80
-0.05
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 26 DAC Filter Frequency Response - Type 2
0
Figure 27 DAC Filter Ripple - Type 2
0
-0.05
-20
Response (dB)
Response (dB)
-40
-0.1
-60
-0.15
-80
-0.2
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 28 DAC Filter Frequency Response - Type 3
Figure 29 DAC Filter Ripple - Type 3
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WM8955L APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Production Data
Figure 30 Recommended External Component Diagram
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WM8955L
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS
To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended.
POWER UP
* * * * * * * * *
Switch on power supplies. By default the WM8955L is in OFF Mode (i.e. only the control interface is powered up) Enable the reference voltage VREF by setting the WM8955L to Standby mode. DO NOT enable any of the analogue outputs at this point. Allow VREF to settle. The settling time depends on the value of the capacitor connected at VMID, and the size of the resistors selected using VMIDSEL ( = RC). Enable DACs, etc. as required. Enable outputs required. Set DACMU = 0 to soft-un-mute the audio DACs.
POWER DOWN
Set DACMU = 1 to soft-mute the audio DACs. Disable outputs. Switch off the power supplies.
LINE OUTPUT CONFIGURATION
All the analogue outputs, LOUT1/ROUT1, LOUT2/ROUT2, and MONOOUT, can be used as line outputs. Recommended external components are shown below.
C1 1uF LOUT2 R1 100 Ohm LINE-OUT SOCKET (LEFT) AGND
WM8955L
ROUT2 C2 1uF R2 100 Ohm
LINE-OUT SOCKET (RIGHT) AGND
Figure 31 Recommended Circuit for Line Output
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1, C2 = 1F: fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly.
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HEADPHONE OUTPUT CONFIGURATION
Production Data
The analogue outputs LOUT1/ROUT1, LOUT2/ROUT2, and OUT3 can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor.
Headphone Output using DC blocking capacitors
DC Coupled Headphone Output (OUT3SW = 00)
LOUT1 ROUT1 WM8955L
C1 220uF
LOUT1 WM8955L
C2 220uF
HPDCEN = 1
ROUT1 HPDC = AVDD/2
HPGND = 0V
Figure 32 Recommended Headphone Output Configurations
When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the OUT3 pin, which must be enabled by setting OUT3 = 1 and OUT3SW = 00. As the OUT3 pin produces a DC voltage of AVDD/2 (=VREF), there is no DC offset between LOUT1/ROUT1 and OUT3, and therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is recommended to connect the DC coupled headphone outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
SPEAKER OUTPUT CONFIGURATION
LOUT2 and ROUT2 can differentially drive a mono 8 speaker as shown below.
LEFT MIXER
LOUT2
WM8955L
ROUT2INV = 1 -1
LOUT2VOL
VSPKR = L-(-R) = L+R
ROUT2
RIGHT MIXER
ROUT2VOL
Figure 33 Speaker Output Connection
The right channel is inverted by setting the ROUT2INV bit, so that the signal across the loudspeaker is the sum of left and right channels.
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WM8955L
PACKAGE DIMENSIONS
FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH DM030.E
CORNER TIE BAR 5 25
D2 B D2/2 32
SEE DETAIL A
D
L 24 EXPOSED GROUND 6 PADDLE A 1 INDEX AREA (D/2 X E/2) E2/2
E2
SEE DETAIL B
E
17
8 2X 16 e 15 B 9 b 2X aaa C aaa C
BOTTOM VIEW
ccc C (A3) 1 A 0.08 C bbb M C A B 1
TOP VIEW
DETAIL A
32x b
CORNER TIE BAR 5
C
SIDE VIEW
SEATING PLANE
1 e/2 TERMINAL TIP
A1
L
43 0. m m 0.5
32x K
DETAIL B
DATUM
66 m m
EXPOSED GROUND PADDLE
R
1 L1
e
Symbols A A1 A3 b D D2 E E2 e L L1 R K aaa bbb ccc REF: MIN 0.85 0 0.18 4.90 3.2 4.90 3.2 0.35
1 b(min)/2 0.20 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-2
Dimensions (mm) NOM MAX 0.90 1.00 0.02 0.05 0.2 REF 0.23 0.30 5.00 5.10 3.3 3.4 5.00 5.10 3.3 3.4 0.5 BSC 0.4 0.45 0.1
L1
R
NOTE
1 2 2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
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PD Rev 4.2 March 2006 45
WM8955L IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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PD Rev 4.2 March 2006 46

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